Alcor, the Egis Group* provides chiplet-based architectural SoC and package design services, targeting the booming markets of HPC, datacenters, AI inference, and Large Language Model applications. Regarding key IP of chiplet-based SoC, it definitely includes very high-speed interface IP (e.g, UCIe die-to-die, PCIe chip-to-chip from the Egis Group) and systematic multi-die architecture based on advanced package technologies (e.g., CoWoS and 2.5D/3D package).
Alcor is competent to offer package feasibility analysis at design early stage, which covers single top die to multi-die (e.g., AI die, HBM die) interconnected interposer die.
This one-stop service saves customers time-to-market from design to manufacturing, especially for tsmc CoWoS flow.

*Subsidiaries of the Egis.

Chiplet

• Top die Design Candidates: CPU / XPU
  / AI Accelerator
• tsmc CoWoS Rule feasibility analysis
• IP/SoC PPA analysis
• HBM Solution Consultant
• HBM consigned Flow Management
• One-stop top die design service
  (spec-in / co-sim / tape-out / manufacturing)

Chip on Wafer
(interposer) (CoW)

• CoWoS Floorplan Architecture Analysis
• Interposer Physical Design
• Interposer Vendor Option
• Interposer Testing
• Dummy die Vendor Option
• CoW Flow Management

On Substrate (oS)

• Substrate Architecture Design Analysis
• Package Design
• Package Simulation
• Probe Card Wafer Testing
• CoWoS Testing
• Manufacturing Management