DDR and LPDDR Combo PHY
Our DDR and LPDDR Combo PHY is a versatile and high-performance solution designed to meet the memory interface needs of modern computing systems. This multi-standard PHY supports different types of DDR and LPDDR, providing flexibility and future-proofing for various applications including high-performance computing, mobile devices, and data centers. It ensures robust performance with high data rates, low latency, and efficient power consumption.
Key Features
Supports multiple combinations of DDR/LPDDR interfaces
- DDR3, DDR3L, DDR4 and LPDDR4 combo PHY
- LPDDR4X and LPDDR5 combo PHY
- LPDDR5 and LPDDR5X combo PHY
- DDR4, DDR5 and LPDDR4 combo PHY
- DDR4, DDR5, LPDDR4, LPDDR4X combo PHY
- Etc.
Compliant with JEDEC DDR and LPDDR standards
Supports all auto calibrations
- Impedance calibration
- Delay measurement for clock period
- Write-leveling and gate training (per DRAM specification)
- Read and Write data eye training
- Per-bit, per-rank delay controllable (including CA/DQ/DQS)
- Etc.
Industry leading area and power
Robust Signal Integrity: Advanced equalization and timing features to ensure reliable data transmission
Supports DDR/LPDDR I/O with power-down retention
Supports CA and DQ signal swap table for easy system integration
Supports LPDDR Dynamic Voltage and Frequency Scaling (DVFS)
Compliant with AMBA APB3.0 for register accessing
LPDDR5X PHY
Our LPDDR5X PHY is a cutting-edge, high-performance physical layer interface PHY designed to meet the demanding requirements of modern computing and mobile applications. This PHY supports the latest LPDDR5X standard, providing enhanced data rates, lower latency, and improved power efficiency. It is ideal for applications such as smartphones, tablets, laptops, and high-performance computing systems, where speed and energy efficiency are paramount.
Key Features
Supports High Data Rate
- 8,533 MT/s (5nm and 3nm)
- 6,400 MT/s (16nm and 12nm)
Compliant with JEDEC LPDDR5X standards
Scalable Architecture: Supports multiple channels and ranks, offering flexibility for various memory configurations
Supports all auto calibrations
- Impedance calibration
- Delay measurement for clock period
- Write-leveling and gate training (per DRAM specification)
- Read and Write data eye training
- Per-bit, per-rank delay controllable (including CA/DQ/DQS)
- Etc.
